1. Field of the Invention
This application is a continuation of U.S. Pat. application No. 08/951,814, filed Oct. 14, 1997, which is a continuation of U.S. Pat. No. 6,088,526 issued Jul. 11, 2000.
The present invention is directed to the field of programmable gate arrays. More particularly, the present invention is directed to a scalable multiple level connector tab network for increasing routability and improving speed of signals in a field programmable gate array.
2. Art Background
A field programmable gate array (FPGA) is a cost effective, high density off the shelf integrated logic circuit which can be programmed by the user to perform logic functions. Circuit designers define the desired logic functions and the FPGA is programmed to process the signals accordingly. Depending on logic density requirements and production volumes, FPGAs are superior alternatives in terms of cost and time to market. A typical FPGA essentially consists of an outer ring of I/O blocks surrounding an interior matrix of configurable function generator (CFG) logic blocks. The I/O blocks residing on the periphery of an FPGA are user programmable such that each I/O block can be programmed independently to be an input or an output and can also be tri-statable. Each logic block typically contains CFGs and storage registers. The CFGs are used to perform boolean functions on its input variables.
Interconnect resources occupy the channel between the rows and columns of the matrix of logic blocks and also between the logic blocks and I/O blocks. These interconnect resources provide flexibility to control the interconnection between two or more designated points on the chip. Usually a metal network of lines is oriented horizontally and vertically in rows and columns between the logic blocks. Programmable switches connect inputs and outputs of the logic blocks and I/O blocks to these metal lines. Cross point switches and interchanges at the intersection of the rows and columns are used to switch signals from one line to another. Often long lines are used to run the entire length and/or breadth or the chip in order to provide point to point connectivity. The functions of the I/O logic blocks and their respective interconnections are all programmable. Typically, these functions are controlled by a configuration program stored in an on-chip or separate memory.
As technology has become more and more sophisticated so has the functionality of FPGAs. The number of CFGs in an array has increased providing for more complex logic functions. It follows that the number of interconnection resources also has increased. Competing with the increased number of CFGs and interconnecting resources is the need to keep the chip as small as possible. One way to minimize the amount of real estate on the chip required is to minimize the routing resources while maintaining a certain level of interconnectivity. Therefore, it can be seen that as the functionality implemented on the chip increases, the interconnection resources required to connect a large number of signals can be quickly exhausted. As a consequence, most CFGs are either left unused due to inaccessibility or the CFGs are used simply to interconnect wires instead of performing certain logic functions. This can result in unnecessarily long routing delays and low logic utilization. The alternative is to provide more routing resources which can increase the chip die size dramatically.